পরিশিষ্ট:কম্পিউটার স্থাপত্য পরিভাষা
- Desktop computer
- Server
- Supercomputer
- Terabyte
- Embedded computer
- Systems software
- Operating System
- Compiler
- Binary digit: বাইনারি সংখ্যা
- Assembler
- Assembly language
- High-level programming language
- Input device
- Output device
- Cathode ray tube
- Pixel
- Flat panel display
- Liquid crystal display
- Active matrix display
- Motherboard
- Integrated Circuit
- Memory
- Central Processor Unit
- DIMM (Dual Inline Memory Module)
- Instruction Set Architecture
- Application binary interface (ABI)
- Implementation
- Volatile memory
- Nonvolatile memory
- Primary memory
- Secondary memory
- Magnetic disk
- Hard disk
- Megabyte
- Floppy disk
- Transistor
- Vacuum
- Local Area network
- Wide Area network
- Very Large Scale Integrated (VLSI) Circuit
- Silicon সিলিকন
- Semiconductor অর্ধ-পরিবাহী
- Silicon Crystal Ingot
- Wafer
- Defect
- Die
- Yield
- Instruction set
- Stored-program concept
- Word
- Data transfer instruction
- Address
- Alignment restriction
- Machine language
- Instruction format
- Opcode
- NOT
- NOR
- Conditional branch
- Basic block
- Jump address table/Jump table
- Procedure
- Jump-and-link instruction
- Return address
- Program counter
- Caller
- Callee
- Stack
- Stack pointer
- Global pointer
- Procedure frame
- Activation record
- Frame pointer
- Text segment
- PC-relative addressing
- Addressing mode
- Pseudoinstruction
- Symbol table
- Linker
- Link editor
- Executable file
- Loader
- Java bytecode জাভা বাইটকোড
- Java virtual machine (JVM)
- Just In Time compiler (JIT)
- Loop unrolling
- Object-oriented language
- General-purpose register
- Least significant bit
- Most significant bit
- Biased notation
- Exception
- Interrupt
- Dividend
- Divisor
- Quotient
- Remainder
- Scientific notation
- Normalized
- Floating point
- Fraction ভগ্নাংশ
- Exponent সূচক
- Overflow (floating-point)
- Underflow (floating-point)
- Double precision
- Single precision
- Guard
- Round
- Units in the last place (ULP)
- Sticky bit
- Response time
- Execution time
- CPU execution time
- User CPU time
- System CPU time
- Clock Cycle
- Clock period
- Clock cycles per instruction
- Instruction unit
- Workload
- Arithmetic mean
- Weighted Arithmetic mean
- System Performance Evaluation Cooperative (SPEC) benchmark
- Amdahl’s law
- Million instructions per second (MIPS)
- State element
- Clocking Methodology
- Edge-triggered clocking
- Control signal
- Datapath element
- Program Counter
- Register file
- Sign-extend
- Branch tagset address
- Branch taken
- Branch not taken
- Delayed branch
- Don’t care term
- Single-cycle implementation
- Multicycle implementation
- Microprogram
- Finite state machine
- Next state function
- Vectored interrupt
- Microprogrammed control
- Hardwired control
- Microcode
- Superscalar
- Microinstruction
- Micro-operations
- Trace cache
- Pipelining
- Structural hazard
- Data hazard
- Forwarding
- Bypassing
- Load-use data hazard
- Pipeline stall
- Control hazard
- Branch hazard
- Untaken branch
- Branch prediction
- Latency (pipeline)
- Nop
- Flush (instructions)
- Dynamic branch prediction
- Branch prediction buffer
- Branch history table
- Branch delay slot
- Branch target buffer
- Correlating predictor
- Tournament branch predictor
- Imprecise interrupt
- Precise interrupt
- Precise exception
- Instruction-level parallelism
- Multiple issue
- Static multiple issue
- Dynamic multiple issue
- Issue slots
- Speculation
- Issue packet
- Register renaming
- Antidependence
- Name dependence
- Instruction group
- Stop
- Predication
- Poison
- Advanced load
- Dynamic pipeline scheduling
- Commit unit
- Reservation station
- Reorder buffer
- In-order commit
- Out-of-order execution
- Microarchitecture
- Architectural registers
- Instruction latency
- Temporal locality
- Spatial locality
- Memory hierarchy
- Block
- Hit rate
- Miss rate
- Hit time
- Miss penalty
- Direct-mapped cache
- Tag
- Valid bit
- Cache miss
- Write-through
- Write buffer
- Write-back
- Split cache
- Fully associative cache
- Set-associative cache
- Least recently used (LRU)
- Multilevel cache
- Global miss rate
- Local miss rate
- Virtual memory
- Physical address
- Protection
- Page fault
- Virtual address
- Address translation
- Segmentation
- Page table
- Swap space
- Reference bit
- Translation-lookaside buffer
- Virtually addressed cache
- Aliasing
- Physically addressed cache
- Kernel mode
- Supervisor mode
- System call
- Context switch
- Exception enable
- Restartable instruction
- Handler
- Unmapped
- Three Cs model
- Compulsory miss
- Cold start miss
- Capacity miss
- Conflict miss
- Collision miss
- Nonblocking code
- I/O requests
- Nonvolatile
- Track
- Sector
- Seek
- Rotation latency
- Small computer systems interface (SCSI)
- Redundant array of inexpensive devices (RAID)
- Striping
- Mirroring
- Protection group
- Hot swapping
- Standby spares
- Bus transaction
- Processor-memory bus
- Backplane bus
- Synchronous bus
- Asynchronous bus
- Handshaking protocol
- Split transaction protocol
- Memory-mapped I/O
- I/O instructions
- Polling
- Interrupt-driven I/O
- Direct Memory Access (DMA)
- Bus master
- Transaction processing
- I/O rate
- Data rate